| 摘要 |
A data driver including a shift register unit configured to receive a first clock signal, a second clock signal, and a start pulse, and to generate a sampling pulse, a sampling latch unit configured to receive and output bits and reversed bits of digital data, in correspondence with the sampling pulse, a holding latch unit configured to receive the bits and reversed bits output by the sampling latch unit, and to output the bits and reversed bits, in correspondence with a first enable signal and a second enable signal, and a digital-to-analog converter configured to receive the bits and reversed bits output by the holding latch unit and to generate an analog signal corresponding to values of the received bits and reversed bits.
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