发明名称 |
Indirect measurement of negative margin voltages in endurance testing of EEPROM cells |
摘要 |
An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled to a power supply ground. A gate of the first transistor is further coupled to a source of the first transistor. A second transistor is coupled in series with a memory cell with a source of the second transistor coupled to a positive power supply voltage and a gate of the second transistor is coupled to the drain of the first transistor.
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申请公布号 |
US2007237013(A1) |
申请公布日期 |
2007.10.11 |
申请号 |
US20060393551 |
申请日期 |
2006.03.29 |
申请人 |
NG PHILIP S;LE MINH V;WANG LIQI;SON JINSHU |
发明人 |
NG PHILIP S.;LE MINH V.;WANG LIQI;SON JINSHU |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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