| 摘要 |
A memory cell (10, 12, 14, 16) has a first (22) and second (20) conductor. The first conductor (22) is oriented in a first direction and the second conductor (20) is oriented in a second direction. The first conductor has at least one edge (36, 38, 42). A state-change layer (24) is disposed on the first conductor and a control element (26) is partially offset over the at least one edge of the first conductor. The control element is disposed between the first and second conductors. Preferably the state-change layer is a direct-tunneling or dielectric rupture anti-fuse. A memory array (18) can be formed from a plurality of the memory cells. Optionally, creating multiple layers of the memory cells can form a three-dimensional memory array (see Fig. 7). |
