摘要 |
PROBLEM TO BE SOLVED: To provide a generation device or the like for generating a test vector set, capable of reducing the difference between each logic value generated before and after scan capture, concerning the output of a scan cell included in a full-scan sequential circuit. SOLUTION: This generation device 200, that generates an initial test vector set 216 to a logic circuit, is equipped with an object test vector specifying part 204 for specifying a test vector to be selected, by satisfying a prescribed standard, relative to the number of bits (number of transition bits) wherein the difference between each logic value is generated, before and after the scan capture, concerning the output of the scan cell included in the order circuit in each test vector, in the initial test vector set 216; and a test vector set transformation part 206 for transforming the test vector to be selected, specified by the object test vector specifying part 204 so that the number of transition bits is reduced, concerning the output of the scan cell included in the sequential circuit. COPYRIGHT: (C)2008,JPO&INPIT
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