| 摘要 |
In accordance with the teachings of the present invention, a system and method for optimizing DRAM refreshes in a multi-channel memory controller are provided. In a particular embodiment, the method includes receiving, at a router in a light modulation system, a signal from one of a plurality of channels operable to read or write to a plurality of DRAM banks, the signal indicating that the channel does not need to access the plurality of DRAM banks during predetermined time period. The method also includes indicating the receipt of the signal to a refresh channel including a plurality of counters, wherein each counter is operable to track refreshes of a respective one of the plurality of DRAM banks. The method further includes receiving, from the refresh channel, an indication of one of the plurality of DRAM banks to refresh in response to the receipt of the signal, and refreshing the indicated DRAM bank.
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