发明名称 Range pattern definition of susceptibility of layout regions to fabrication issues
摘要 A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at least one set of values that identify a maximum limit and a minimum limit (i.e. the range) between which relative location and/or dimension of an additional line segment of the pattern in a portion of a layout of an integrated circuit (IC) chip, represents a defect in the IC chip when fabricated. In most embodiments, multiple ranges are specified in such a range defining pattern for example a width range is specified for the width of a trace of material in the layout and a spacing range is specified for the separation distance between two adjacent traces in the layout.
申请公布号 US2007240086(A1) 申请公布日期 2007.10.11
申请号 US20060394466 申请日期 2006.03.31
申请人 SYNOPSYS, INC. 发明人 SINHA SUBARNAREKHA;CHIANG CHARLES C.
分类号 G06F17/50 主分类号 G06F17/50
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