| 摘要 |
Methods and apparatus are provided for modeling and synthesizing circuits for packet processing that transform one or more fields of a packet. A circuit for packet processing that transforms one or more fields of a packet is modeled by representing the transformation using a packet editing graph having at least one node. The transformation can comprise one or more of adding, removing, modifying and maintaining the at least one field of a packet header. A circuit for packet processing that transforms one or more fields of a packet is synthesized by synthesizing a control finite state machine based on the packet editing graph, wherein the packet editing graph represents the circuit for packet processing. Elements of the packet editing graph are transformed in a predefined manner into corresponding elements of the synthesized circuit for packet processing.
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