| 摘要 |
An image data processing circuit including: an input section for inputting image data; a plurality of compressing sections which are capable of compressing the input image data solely or in parallel; a plurality of decompressing sections which are capable of decompressing the compressed image data solely or in parallel; an output section for outputting the decompressed image data; a transferring section for transferring image data between a memory and of the input section, the compressing sections, the decompressing sections and the output section individually; and a transfer controlling section for selecting a mode from a parallel input/output mode, a parallel input mode and a parallel output mode. |
