DECORDING CIRCUIT AND DISPLAY APPARATUS

摘要

A decoding circuit and a display apparatus are provided to generate an analog voltage signal by performing a high speed decoding operation on input data based on reduced numbers of switching elements. A decoding circuit includes a first bit group decoding circuit(FBD), which selects and outputs an output candidate from plural output candidates corresponding to a decoding result by decoding a bit of a first bit group. The first bit group decoding circuit includes first sub-decoding circuits(FSB), which select one of output candidate groups by receiving a bit of the first bit group. Multi-bit digital data are divided into plural bit groups. The plural bit groups include the first bit group and dispose a bit group decoding circuit. The bit group decoding circuit includes the first bit group decoding circuit. Each of the first sub-decoding circuits includes plural unit decoders. A final bit group decoding circuit(LBD) includes plural final sub-decoding circuits(LSD), which select a corresponding output of the bit group decoding circuit and deliver the selected output to an output signal line.