| 摘要 |
In a method of generating an internal clock for a semiconductor memory device, a doubled clock is generated during operation in a high-speed test mode in response to an external clock. A data clock is generated by delaying the doubled clock so that data read from a memory cell array in the semiconductor memory device is output in synchronization with the external clock. A doubled sync clock synchronized with the external clock is generated by delaying the data clock. An internal clock is generated during operation in the high-speed test mode by delaying the doubled sync clock by a delay amount that corresponds to a delay amount experienced in generation of an internal clock in response to the external clock during operation in a normal mode. Accordingly, the high-speed test operation of the semiconductor memory device can be efficiently performed.
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