发明名称 Method and apparatus for biasing a metal-oxide-semiconductor capacitor for capacitive tuning
摘要 A method and apparatus is presented for generating a reference voltage that biases a metal-oxide-semiconductor (MOS) transistor used as a varactor in capacitive tuning applications. In one embodiment, a biasing circuit is implemented. The biasing circuit comprises a diode-clamped FET and an element coupled to the diode-clamped FET at a connection point. The element produces a constant current through the diode-clamped FET. A voltage is produced at the connection point. The voltage is one gate overdrive plus a threshold voltage above ground or one gate overdrive plus a threshold voltage below VDD. Establishing a threshold voltage in this way enables the biasing circuit to track an ideal voltage of a varactor that is coupled to the biasing circuit through the threshold voltage.
申请公布号 US7280002(B2) 申请公布日期 2007.10.09
申请号 US20050070985 申请日期 2005.03.03
申请人 AVAGO TECHNOLOGIES GENERAL IP PTE LTD 发明人 LOKE ALVIN LENG SUN;WEE TIN TIN;BARNES ROBERT KEITH;ARAVE KARI LEE;CYNKAR THOMAS EDWARD;PFIESTER JAMES RUHL
分类号 H03B5/12 主分类号 H03B5/12
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