发明名称 Methods for wafer level burn-in
摘要 A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. Methods may also include using a super voltage level to signal a transition between cycles of burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. Unused registers of nonvolatile elements may also be determined by reading the nonvolatile element registers on a semiconductor die on the wafer. Circuits and systems associated with the method of the present invention are also disclosed.
申请公布号 US7279918(B2) 申请公布日期 2007.10.09
申请号 US20060527047 申请日期 2006.09.26
申请人 发明人
分类号 G01R31/26 主分类号 G01R31/26
代理机构 代理人
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