发明名称 Phase-locked loop
摘要 A phase-locked loop includes an oscillator, a phase detector coupled to the oscillator, a charge pump coupled to the phase detector, a filter coupled to the charge pump, a voltage controlled oscillator, and a fractional frequency divider. The voltage controlled oscillator sends a VCO signal to the divider which sends an output signal to the phase detector. The divider comprises a prescaler that divides the VCO signal by an integer number and the divider emits a first signal representing the result of the division. The phase-locked loop comprises an accumulator coupled to the divider and a digital-analog converter that receives the first signal and outputs a DAC signal aligned with the first signal. The phase-locked loop comprises a circuit coupled to the digital-analog converter and to the prescaler to synchronize the DAC signal with a signal output from the prescaler.
申请公布号 US7279993(B2) 申请公布日期 2007.10.09
申请号 US20050239654 申请日期 2005.09.29
申请人 STMICROELECTRONICS S.R.L. 发明人 BRUNO ANGELA;CALI' GIOVANNI;PALLESCHI ANTONIO
分类号 H03L7/00;H03L7/06 主分类号 H03L7/00
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