| 摘要 |
PROBLEM TO BE SOLVED: To synchronize and output a timing signal in an LSI circuit which achieves high speed operation of the signal by data multiplexing. SOLUTION: In a high speed operation of the signal by multiplexing of output data in a plurality of LSI circuits, a FiFo function of a buffer memory which absorbs phase difference of a data low speed unit for every output data is prepared, when a step number of the FiFo is reduced without assuring the maximum return time, a read-out cycle control circuit is prepared, which performs read-out cycle control according to circuit data output in which return time of a frequency divide start signal to the FiFo is most late, a hysteresis characteristic is given to comparing timing of operation stage switching in the FiFo, and the stage switching operation is stabilized. COPYRIGHT: (C)2008,JPO&INPIT
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