| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a magnetic memory cell which can promote high integration while suppressing the write disturb in MRAM. <P>SOLUTION: The magnetic memory cell is used as equipped with transistors TR1, TR2 and a magnetic resistance element group 2. The gate of the transistor TR1 is connected to a word line WL1, and its first source/drain to a bit line BL1. The gate of the transistor TR2 is connected to the word line WL1, and its third source/drain to a bit line BL2. The magnetic resistance element group 2 is equipped with a plurality of magnetic resistance elements MTJ to which a conductor through which a writing current passes is connected in series or in parallel each other, one side of the conductor is connected to a second source/drain of TR1 and another side to a fourth source/drain electrode of TR2, one side in the plurality of magnetic resistance elements MTJ is connected to the conductor and another side to a word line WL2, and information is memorized in the combination of direction of magnetization of the plurality of magnetic resistance elements MTJ. The plurality of the magnetic resistance elements MTJ have different resistance values mutually. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
