| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device for reliability evaluation, capable of contriving shortening of the time for evaluation and analysis, while further improving the evaluation and analysis, in the semiconductor device for reliability evaluation which is equipped with a memory circuit comprising a flip flop. SOLUTION: The device is manufactured by a layout rule that is more relaxed than that of the memory circuit 10 and is equipped with a mitigation layout cell circuit 1, having at least a buffer 13. Furthermore, a plurality of upper layer wiring patterns 40a, 40b, 40c, 40d are formed for propagating the output signal from the memory circuit 10 or the mitigation layout cell circuit 1 to the upper layer side of the multilayers wiring structure. Furthermore, a selection circuit 43 is equipped for selectively extracting the output signal from the memory circuit 10 detouring a plurality of respective upper layer wiring patterns 40a, 40b, 40c, 40d or the mitigation layout cell circuit 1. COPYRIGHT: (C)2008,JPO&INPIT
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