| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device in which planarity of an interconnection forming layer is ensured in planarization processing performed during an interconnection forming process, and circuit simulation can be performed with high precision by reducing capacitance between the interconnection and dummy wiring. SOLUTION: In the signal interconnection forming layer 13 of (N+1)th layer, dummy wiring 44 thinner than the signal interconnections 17-20 is formed in flush with the upper surface of the signal interconnections 17-20 of (N+1)th layer. The signal interconnection layer 11 of Nth layer is arranged similarly. COPYRIGHT: (C)2008,JPO&INPIT
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