SHARED-MEMORY SWITCH FABRIC ARCHITECTURE

摘要

A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns and is characterized by a second data rate. Non-blocking receive and transmit crossbar circuitry is operable to connect any of the receive and transmit ports, respectively, with any of the memory banks. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to facilitate striping of each data segment of a frame across the memory banks in one of the rows, and to facilitate striping of successive data segments of the frame across successive rows in the array.