发明名称 SHAPER CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a shaper circuit applicable to transmission devices of different bandwidth or accuracy. <P>SOLUTION: The shaper circuit comprises a parameter storage, a dequeue subtractor, an add-token summing portion, a max token comparator, and a dequeue permission determining portion. The dequeue subtractor subtracts a packet length to be dequeued from a current token read from the parameter storage, and stores the result in the parameter storage. The add-token summing portion adds an add-token read from the parameter storage to the current token read from the parameter storage for each constant token addition period, and stores the result in the parameter storage. The max token comparator checks so that the summation result of the add-token summing portion does not exceed a max token read from the parameter storage. The dequeue permission determining portion outputs a dequeue permission request if the subtraction result of the dequeue subtractor is equal to or more than 0 (zero), or outputs a dequeue permission request if the summation result of the add-token summing portion is equal to or more than 0 (zero). In addition, the number of bits is set to a variable value for the current token, the add-token, and the max token in the parameter storage, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2007259068(A) 申请公布日期 2007.10.04
申请号 JP20060080802 申请日期 2006.03.23
申请人 FUJITSU LTD 发明人 OTA YOKO;IMAMURA KATSUMI;KUROKAWA YASUSHI;FUKUNAGA HIDEYO
分类号 H04L12/813;H04L12/815;H04L12/819 主分类号 H04L12/813
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