发明名称 Power manager with selective load reduction
摘要 In some embodiments, a power manager may be coupled to a load circuit and configured to receive an input signal indicating a line disturbance on a power supply line and to reduce a load requirement of the load circuit in accordance with the received signal. The power manager may be configured to selectively reduce power to components with low entrance latency while continuing to provide full power to components with high entrance latency. Other embodiments are disclosed and claimed.
申请公布号 US2007228832(A1) 申请公布日期 2007.10.04
申请号 US20060396190 申请日期 2006.03.31
申请人 PRATT ANNABELLE;GORBATOV EUGENE;KUMAR PAVAN;ALDRIDGE TOMM V 发明人 PRATT ANNABELLE;GORBATOV EUGENE;KUMAR PAVAN;ALDRIDGE TOMM V.
分类号 H02J3/14;G05D11/00 主分类号 H02J3/14
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