| 摘要 |
<p>A manufacturing method for an array of polysilicon fins built up into fin blocks (29) that are aligned in a comb-like array occupying a wafer (11) surface. By subsurface and supersurface contact, fin blocks can be arranged into components or even systems. The method involves wafer area masking and etching over the wafer surface without step-and-repeat lithography, In an exemplary embodiment, an EEPROM memory array has memory cells that combine a floating gate transistor and a select transistor into a single cell. The floating gate (29) has a tunnel oxide (41) window (91) distal to the 'wafer substrate and facing an erase electrode (97) while a capping control gate electrode (103) has a portion next to the floating gate. The control gate and the floating gate have portions between source {61} and drain (63) electrodes for communicating with the channel (104) therebetween, The control gate and the erase gate have supersurface contacts to memory array word lines (CG and EG) while che subsurface source and drain electrodes are extended to memory array bit lines (BL) .</p> |
