发明名称 MASTER COMMUNICATION CURCUIT, SLAVE COMMUNICATION CURCUIT, AND DATA COMMUNICATION METHOD
摘要 A master communication circuit, a slave communication circuit, and a data communication method are provided to transceive data even when the number of terminals needed for communication is small and precision of a clock is low. A timer circuit(25) detects a first time. A first output circuit enables the timer circuit to start a detecting operation and outputs a first output signal of one-side logical level for starting the detecting operation for a second time longer than the first time of the slave communication circuit(2) if a value transmitted to the slave communication circuit is one-side logical level. A second output circuit outputs a second output signal of another logical level if the timer circuit detects the first time. A value of one-side logical level is transmitted to the slave communication circuit by preventing the slave communication circuit from detecting the second time, enabling the timer circuit to detect the first time, and enabling the second output circuit to output the second output signal.
申请公布号 KR20070097349(A) 申请公布日期 2007.10.04
申请号 KR20070029815 申请日期 2007.03.27
申请人 SANYO ELECTRIC CO., LTD. 发明人 YAMADA SUSUMU
分类号 G06F13/38;G06F15/163 主分类号 G06F13/38
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