发明名称 Error diffusion processing circuit and method, and plasma display device
摘要 An error diffusion processing circuit is provided which has a separator dividing digital pixel data of an object pixel into high bits and low bits, and making the low bits error data, multiplier circuits multiplying transmission error data of a plurality of adjacent pixels by adjacent pixel weighting coefficients, and outputting weighted transmission error data, a first adder circuit performing addition on the basis of the error data of the object pixel, and the weighted transmission error data of adjacent pixels, and outputting an added value and a carry value, a second adder circuit adding the high bit pixel data of the object pixel and the carry value, and outputting output pixel data, and a correction circuit correcting transmission error data of an adjacent pixel to the error data of the object pixel or data obtained by performing arithmetic processing of it when the transmission error data of the adjacent pixel is 0, and outputting it to the corresponding multiplier circuit.
申请公布号 US2007230813(A1) 申请公布日期 2007.10.04
申请号 US20060358740 申请日期 2006.02.22
申请人 FUJITSU HITACHI PLASMA DISPLAY LIMITED 发明人 YAMAMOTO AKIRA;TAJIMA MASAYA;UEDA TOSHIO
分类号 G06K9/36;G09G3/20;G09G3/28;G09G5/00;H04N1/405 主分类号 G06K9/36
代理机构 代理人
主权项
地址