发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit in which there is no influence of a spurious signal, a circuit size to be added is small, and a lock-up time is shortened. SOLUTION: A phase difference signal detected by a phase comparison circuit is connected to a charge pump with a switch 1 which is cut by an external trigger, output of the charge pump drives a voltage controlled oscillation circuit through a low pass filter and through a switch 2 which is cut by the external trigger, furthermore, the output of the charge pump is inputted to a voltage follower. The voltage follower drives the voltage controlled oscillation circuit through a switch 3 connected by the external trigger; a frequency divider installs an initialize terminal, and outputs a feedback signal; an output of a flip-flop circuit is connected to the initialize terminal of the frequency divider; and the flip-flop circuit cancels the initialization of the frequency divider by the reference signal when the external trigger is not inputted, and keeps its state, is initialized by the reference signal when the external trigger is inputted, and output a signal to keep the state. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007259215(A) 申请公布日期 2007.10.04
申请号 JP20060082491 申请日期 2006.03.24
申请人 TOPPAN PRINTING CO LTD 发明人 TSUSHIMA HIROYUKI
分类号 H03L7/10;H03L7/199 主分类号 H03L7/10
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