| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock phase discriminator that is applicable even to a phase modulation system having no zero cross point during data transition like offset QPSK or the like. <P>SOLUTION: A differential device 24 calculates a difference between an additional value of adding sample data, which are obtained by sampling an eye pattern with a Sample CLK, by four and a value obtained by delaying the additional value by one Sample CLK. A code inverter 25 inverts a code of an output value of the differential device 24. A selector 27 selects the output value of the code inverter 25 when the eye pattern continuously has a negative polarity, and also, it selects an output value of the differential device 24 in the case other than that. An AND circuit 33 masks the output value of the selector 27 when the polarity of the eye pattern is inverted except a case when the polarity of the eye pattern is inverted immediately after the time when the eye pattern continuously has the same polarity, and also, it gives the output value of the selector 27 to a flip-flop 34 in the case other than that. <P>COPYRIGHT: (C)2008,JPO&INPIT |
