发明名称 3:2 Bit compressor circuit and method
摘要 A circuit to convert three input bits (A, B and C) to a redundant format may include a first block with at least one transmission gate, and a second block with at least one static mirror. The first block may receive the three bits and output a sum bit, and the second block may receive the three bits and output a carry bit.
申请公布号 US2007233760(A1) 申请公布日期 2007.10.04
申请号 US20060392070 申请日期 2006.03.29
申请人 MATHEW SANU;KRISHNAMURTHY RAM;GUO ZHENG 发明人 MATHEW SANU;KRISHNAMURTHY RAM;GUO ZHENG
分类号 G06F7/00;G06F15/00 主分类号 G06F7/00
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