发明名称 Method for post-routing redundant via insertion in integrated circuit layout
摘要 The objective of the invention is to provide a method for post-routing redundant via insertion. The method is to construct a conflict graph from a post-routing design first, to find a maximal independent set (MIS) of the conflict graph, and to replace a single via with a double via for each vertex in the maximal independent set. Furthermore, since redundant vias can be classified into on-track and off-track ones and since on-track ones have better electrical properties, the invention also presents two methods to increase the amount of on-track redundant vias while a redundant via insertion solution is given.
申请公布号 US2007234258(A1) 申请公布日期 2007.10.04
申请号 US20060391628 申请日期 2006.03.28
申请人 NATIONAL TSING HUA UNIVERSITY 发明人 LEE KUANG-YAO;WANG TING-CHI
分类号 G06F17/50 主分类号 G06F17/50
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