| 摘要 |
PROBLEM TO BE SOLVED: To perform a speed test of a receiver circuit, without the connections of the driver circuit. SOLUTION: Responding to a delay control signal, a delay section 3 performs delay control of the phase of clock input signal and outputs it. In an actual speed test, a selector 2 selects and outputs a clock input signal inputted from the delay section 3, from between the clock input signal and an input signal from an external terminal. A serial-to-parallel converter 4 samples the signal outputted from the selector 2 on the basis of a sampling clock signal, converts a serial signal into a parallel signal type, and outputs it. A clock data recovery circuit 5 generates a sampling clock signal of an optimum phase, corresponding to the output signal 7 of the converter 4, and supplies it to the converter 4. By monitoring a control code 60 that controls the phase of the sampling clock, delay variation amount and code variation amount are correlated, and actual speed test is performed. COPYRIGHT: (C)2008,JPO&INPIT
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