发明名称 NON-TEMPORAL MEMORY REFERENCE CONTROL MECHANISM
摘要 An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.
申请公布号 US2007234008(A1) 申请公布日期 2007.10.04
申请号 US20070758515 申请日期 2007.06.05
申请人 IP-FIRST, LLC 发明人 HENRY G. G.;HOOKER RODNEY E.;PARKS TERRY
分类号 G06F9/30;G06F9/22;G06F9/318;G06F9/38;G06F12/08 主分类号 G06F9/30
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