| 摘要 |
A phase locked loop has two detecting circuits 310 and 320. The first circuit 310 includes a phase detector 310 configured to detect a phase difference between leading edges of an input signal and a feedback signal. The second circuit 320 includes a second phase detector 305 configured to detect a phase difference between trailing edges of the input signal and the feedback signal. The first circuit 310 also includes a charge pump 302 with an adjustable current source 3021, by which the bandwidth of the loop is adjusted. The second circuit 320 also includes a charge pump 306 with a fixed current source 3061 and an adjustable current source 3062, by which the bandwidth of the loop is adjusted. The invention provides fast phase lock, low jitter, duty cycle correction and adjustable bandwidth. |
