| 摘要 |
1,063,003. Bi-stable circuits. GENERAL ELECTRIC CO. May 25, 1965 [June 29, 1964], No. 22079/65. Heading H3T. A bi-stable circuit with crosscoupled transistors has input data applied via a circuit device to the collector of one transistor and clock pulses applied to both emitters. In Fig. 1 binary data signals of +2 v. (" 0 ") or +4 v. (" 1 ") are applied via resistor 23 to the collector of transistor 11 and a fixed voltage of + 3 v. is applied via resistor 25 to the collector of transistor 17 so that transistor 11 conducts in the " 0 " state and 17 conducts in the " 1 " state. Narrow " read-in " clock pulses of + 4 v. are applied at 44 to the emitters at times during the occurrence of the data signals and cause the circuit to change over as appropriate. The charge on the base-collector capacitance 40 or 41 of the non- conducting transistor supplies additional base current to speed up the change even if the clock pulse has a sloping edge. The data bit registered can be read out at terminal 35 or its complement at terminal 55. If the latter facility is not required resistor 59 can be replaced by a direct connection. For some transistors both resistors 29 and 59 can be replaced by direct connections. Further binary signals can be read in at terminal 26, e.g. the complements of those applied at 24. For reading out, the clock pulse has a third level (e.g. - 3 v.) which occurs in between the binary input signals, and this may be used for reading out from a number of bi-stable circuits simultaneously. For this purpose the circuit of Fig. 1 is connected via a diode 31 to the output terminal 34, and other bi-stable circuits are connected to the same point via separate diodes 38. A similar arrangement of diodes 57, 60 can be included at the complementary read-out point. In a modification (Fig. 5, not shown) resistors 23 and 25 are replaced by diodes and a constant current source feeds each collector; this gives faster operation. Either circuit can be constructed in a single chip of material, the emitter, base and collector of each NPN transistor forming separate zones in a block of P-type material. The effect of distributed capacitance between the collectors and the block is avoided by connecting the emitters to the block through a capacitance 78 (Fig. 5, not shown) and applying - 3 v. to the block through an inductance 79. The potential of the block then changes in synchronism with the clock pulses.
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