发明名称 |
Semiconductor memory having dummy bit line precharge/discharge circuit |
摘要 |
Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is controlled according to a change in voltage of the dummy read line DRD which is caused due to the discharge of the precharged dummy read line DRD.
|
申请公布号 |
US7277342(B2) |
申请公布日期 |
2007.10.02 |
申请号 |
US20060480911 |
申请日期 |
2006.07.06 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
SUMITANI NORIHIKO;TSUJIMURA KAZUKI |
分类号 |
G11C7/02 |
主分类号 |
G11C7/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|