| 摘要 |
<p>A method for forming a vernier key in a NAND flash memory device is provided to prevent a vernier key from being damaged by using a high-selectivity recipe with respect to a gate oxide layer in a process for etching a polysilicon layer. A gate oxide layer(102), a polysilicon layer(104) for a floating gate, an etch stop layer(106) and a hard mask layer(108) that are stacked on a semiconductor substrate(100) in which a cell region, a vernier key region and a peripheral circuit region are defined are sequentially etched to form a first trench in the cell region. The etch stop layer and the hard mask layer formed on the semiconductor substrate in the peripheral circuit region are sequentially etched. The polysilicon layer is etched by using a high-selectivity recipe with respect to the gate oxide layer. The gate oxide layer and a part of the semiconductor substrate are etched to form a second trench(114) in the peripheral circuit region. While a first trench formation process is performed on the cell region, the same process as the first trench formation process is performed even on the vernier key region.</p> |
