| 摘要 |
A CDMA receiver with a reduced number of required high speed adders is disclosed. Integration for one symbol period is performed for each value of spreading code corresponding to a particular user signal by the use of a high speed adder (24), first and second switches (25,27), and a register group (26) are used to perform. The integrated values are once stored in respective first registers of the register group (26) and then despread is performed in accordance with respective spreading codes. As a result, an adder (29) with a slow operational speed can be employed as a first slow speed adder for addition of values from first multipliers (280-28m) and a second slow speed adder (30) for addition of the values of the first registers (26). Therefore, a common pilot signal and a user signal can be despread with only one high speed adder (24). <IMAGE> |
