发明名称 |
CLOCK GENERATOR AND CLOCK GENERATING METHOD USING DELAY LOCKED LOOP |
摘要 |
<p>Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second clock signal, a second oscillator to generate a fourth clock signal and a phase frequency detector to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal.</p> |
申请公布号 |
WO2007109225(A2) |
申请公布日期 |
2007.09.27 |
申请号 |
WO2007US06800 |
申请日期 |
2007.03.16 |
申请人 |
GCT SEMICONDUCTOR, INC.;PARK, JOONBAE;LEE, KYEONGHO |
发明人 |
PARK, JOONBAE;LEE, KYEONGHO |
分类号 |
G06F1/04 |
主分类号 |
G06F1/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|