| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress noise while reducing the area in a semiconductor memory where cell bias is controlled under sleep state. <P>SOLUTION: The semiconductor device comprises a memory cell array 11 of a plurality of memory cells arranged in a cell array region, a source potential line for supplying source potential to the memory cell, a switch element group 21 arranged contiguously to the memory cell array 11 in the cell array region and making the source potential line and the ground potential electrically noncontact under sleep state of the memory cell, a p-type first MIS transistor 23 connected between the source potential line and the ground potential and clamping the source potential under sleep state, and a bias formation circuit 22 arranged in the peripheral circuit region on the outside of the cell array region and supplying a bias potential to the gate terminal of the first MIS transistor 23. The first MIS transistor is arranged in the peripheral circuit region. <P>COPYRIGHT: (C)2007,JPO&INPIT |
