| 摘要 |
(Problems) To realize a circuit capable of keeping a constant duty ratio of output isophase multiphase clock signals independently from the duty ratio of input clock signal while minimizing the increase of the number of devices and suppressing the increase of the circuit area of the semiconductor substrate and the increase of the power consumption. (Means for Solving the Problems) In an isophase multiphase clock signal generation circuit according to the present invention, an input clock signal is converted into a ½-frequency-divided complementary clock signal and then is input to a complementary voltage controlled delay device array. The input clock signal is ½-frequency-divided, and therefore becomes a clock signal having a constant duty ratio with no dependency on the duty ratio of the input clock signal. The frequency-divided complementary clock signal is input to the voltage controlled delay device array, and the phase of the complementary output signal from the voltage controlled delay device array is compared with the phase of the frequency-divided complementary clock signal. Thus, isophase multiphase clock signals synchronized with the input clock signal can be output.
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