Stress intermedium engineering

摘要

Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A stressor layer is formed over the transistor. Embodiments include an intermedium layer between the stressor layer and a portion of the transistor. In an embodiment, the intermedium comprises a layer formed between the stressor layer and the gate electrode sidewall spacers. In another embodiment, the intermedium comprises a silicided portion of the substrate formed over the LDS/LDD regions. A transistor that includes the intermedium and, stressor layer has a vertically oriented stress within the channel region. The vertically oriented stress is tensile in a PMOS transistor and compressive in an NMOS transistor.