发明名称 STITCHED MICRO-VIA TO ENHANCE ADHESION AND MECHANICAL STRENGTH
摘要 A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material. The integrated circuit packaging substrate also includes a via for interconnecting the first layer of conductive material and the second layer of conductive material having a base that includes an interfacial adhesion material to stitch the base of the via to a layer of circuitry.
申请公布号 US2007222058(A1) 申请公布日期 2007.09.27
申请号 US20070751312 申请日期 2007.05.21
申请人 INTEL CORPORATION 发明人 LEONG KUM F.;CHUNG CHEE K.;SIM KIAN S.
分类号 H01L23/52;H01L21/48;H01L23/498;H05K3/14;H05K3/38;H05K3/42 主分类号 H01L23/52
代理机构 代理人
主权项
地址