| 摘要 |
<p>An interface circuit for inputting and outputting data and clock of a plurality of speeds includes: an equalizer capable of varying a circuit parameter; a frequency detection unit for detecting a clock frequency; and a parameter calculation control unit for calculating an appropriate circuit parameter by the clock frequency and controlling the equalizer. The frequency detection unit detects at which frequency the interface circuit is currently operating and sends obtained frequency to the parameter calculation control unit. The parameter calculation control unit calculates a circuit parameter of the equalizer so that the interface circuit can operate optimally at the detected frequency and sets the parameter on the equalizer. Thus, it is possible to appropriately control the circuit parameter of the equalizer of the interface circuit and accordingly, it is possible to obtain an optimal operation even if the used interface speed increases or the operation mode is varied.</p> |
