Circuit to reduce internal ESD stress on device having multiple power supply domains

摘要

An ESD protection circuit is designed on an integrated circuit ( 100 ) having a first power supply bus ( 106 ) and a second power supply bus ( 108 ). The circuit includes a first logic gate ( 116, 118 ) having a current path coupled to the first power supply bus. The first logic gate includes an output terminal. A second logic gate ( 122, 124 ) has a current path coupled to the second power supply bus. The second logic gate has an input terminal coupled to the output terminal of the first logic gate. A first device ( 306 ) is coupled in series with the current path of the second logic gate and is always on during normal circuit operation.