| 摘要 |
An internal signal generator is provided to reduce current consumption by controlling on/off of a plurality of flip flop circuits which shift an external signal in response to CAS latency. A plurality of flip flops(102) shifts an external signal in sequence. An enable signal generation part(101) generates enable signals for the flip flops respectively in response to CAS latency. An output part(103) outputs output signals of the flip flops driven in response to the enable signal as an internal signal in response to the CAS latency. The enable signal generation part includes a plurality of individual enable signal generation parts corresponding to the flip flops.
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