发明名称 Phase-locked loop
摘要 A phase-locked loop for adjusting a phase difference between an output signal and an input signal, comprising a phase detector for generating a phase difference signal depending on a phase difference between said output signal and a phase-shifted input signal, a calculator for calculating a signal depending on said phase difference signal and an adjustable offset signal, an oscillator for generating said output signal having an oscillation frequency which is adjusted in response to said calculated signal, and a phase shifter for shifting a signal phase of said input signal by a predetermined phase in response to a control signal to generate said phase-shifted input signal applied to said phase detector.
申请公布号 US2007223639(A1) 申请公布日期 2007.09.27
申请号 US20060386258 申请日期 2006.03.22
申请人 UNTERRICKER REINHOLD 发明人 UNTERRICKER REINHOLD
分类号 H03D3/24 主分类号 H03D3/24
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