| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a PLL circuit for easily generating a PLL clock signal having an arbitrary number of clocks with a logic circuit. <P>SOLUTION: A PLL control signal is input into a flip-flop 7 and is latched in rising a reference clock, thereby generating a PLL clock signal 1 synchronized with the reference clock. Further, the PLL control signal 1 is input into a flip-flop 8 and is latched in rising a dividing signal A, thereby generating a synchronous control signal synchronized with a VCO signal. The synchronous control signal, an arbitrary signal B output from a frequency divider 6, and the VCO signal are input into a PLL clock signal generating signal 9, and a PLL clock signal of a desired clock number can be obtained easily. <P>COPYRIGHT: (C)2007,JPO&INPIT |
