| 摘要 |
A digital-to-time converter (DTC) is provided, made from a plurality of series-connected cells. Each cell has an input interface to accept a signal, a control interface to accept a digital command, a delayed signal path, a minimum delay signal path, and an output interface. The signal path is selected in response to the command. The time delay associated with the delayed signal path of each cell can be varied, so that the plurality of series-connected cells is able to provide a large range of delay combinations. For example, if there are n series-connected cells, then the jth series-connected cell, where j varies from 1 to n, conducts the signal through 2<SUP>j </SUP>MOS gates in the delayed signal path. Assuming a digital control word with n bit places, the jth series-connected cell accepts the jth bit place of the control word to select a delay path.
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