发明名称
摘要 PROBLEM TO BE SOLVED: To actualize a multiplier which can multiply complex numbers and multiply integers with a small hardware quantity. SOLUTION: Data obtained by converting a multiplicand according to the decoding result of a decoder 4 and addition data obtained in a last multiplication cycle are added through the addition of partial adders 10 and 20, and the result is accumulated and stored in partial product registers 32 and 37. The integer of the multiplicand is stored in a multiplicand register 1 and a multiplier is stored in a multiplier register 2. Then the integers are multiplied by each other by repeating a multiplication cycle. The real number part and imaginary part of the complex number of the multiplicand are stored in the high-order and low-order side of the multiplicand register 1, respectively, and the complex number of the multiplier is stored in a multiplier register 2. Then a swapper 3 replaces the high-order side and low-order side of the multiplicand in proper timing, so that complex numbers are multiplied by each other by repeating a multiplication cycle.
申请公布号 JP3982965(B2) 申请公布日期 2007.09.26
申请号 JP19990317986 申请日期 1999.11.09
申请人 发明人
分类号 G06F7/53;G06F17/16;G06F7/52;G06F7/533;G06F17/10 主分类号 G06F7/53
代理机构 代理人
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