Integrated circuit I/O using a high performance bus interface

摘要

The present invention includes a system comprising a bus that includes a plurality of bus lines for carrying substantially all address, data and control information needed by each semiconductor device coupled to the bus for communication with substantially every other semiconductor device connected to the bus, wherein the bus uses address multiplexing to convey a single memory address, a plurality of synchronous dynamic random access memory (DRAM) semiconductor devices coupled to the bus, each DRAM of the plurality of synchronous DRAM semiconductor devices including connection means adapted to connect the DRAM to the bus, clock receiver circuitry for receiving a clock signal, a programmable access-time register for storing a value which is representative of a number of clock cycles of the clock signal to transpire after which the DRAM responds to a read request received synchronously with respect to the clock signal, the programmable access-time register being accessible to the bus through the connection means, wherein data is provided to the programmable access-time register over the bus to set the value in the programmable access-time register, a plurality of output drivers for outputting data onto the bus in response to the read request, wherein the output drivers output the data on the bus after the number of clock cycles of the clock signal transpire and synchronously with respect to the clock signal; so that the read request and the corresponding response are separated by the number of clock cycles as selected by the value stored in the programmable access-time register, wherein each output driver of the plurality of output drivers outputs the data onto the bus at a bus cycle data rate that is twice the rate of the clock signal, sense amplifiers used for reading the data from the memory array, wherein when precharge information received over the bus as a part of the read request indicates that a precharge operation should be performed, automatically precharging the sense amplifiers as a part of execution of the read request, and wherein when the precharge information indicates that a precharge operation should not be performed, holding the data in the sense amplifiers; and a master device coupled to the bus, wherein the master provides the value stored in the programmable access time register, issues the read request that includes precharge information, and receives the data output in response to the read request at the bus cycle data rate after the number of clock cycles as selected by the value stored in the programmable access time register.