发明名称 Gate-coupled ESD protection circuit for high voltage tolerant I/O
摘要 The present disclosure is directed toward electrostatic device protection for semiconductor devices. A circuit for providing electro-static discharge (ESD) protection for a semiconductor circuit may comprise a first circuit coupled to a voltage bus and to the gate of a first transisto, the first circuit comprising a metal-oxide semiconductor (MOS) transistor; and a second circuit coupled to the voltage bus, to ground, and to the gate of the transistor of the first circuit. The MOS transistor of the first circuit may be a PMOS transistor whose source is coupled to the voltage bus, whose drain is coupled to the gate of the first transistor, whose gate is coupled to the second circuit, and whose well is coupled to a floating N-well.
申请公布号 US7274544(B2) 申请公布日期 2007.09.25
申请号 US20040971271 申请日期 2004.10.21
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY 发明人 CHEN KER-MIN;CHIANG CHENG-MING
分类号 H02H9/00 主分类号 H02H9/00
代理机构 代理人
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