发明名称 Bitline exclusion in verification operation
摘要 Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
申请公布号 US7274607(B2) 申请公布日期 2007.09.25
申请号 US20050153188 申请日期 2005.06.15
申请人 MICRON TECHNOLOGY, INC. 发明人 HARTONO HENDRIK;YIP AARON;LOUIE BENJAMIN
分类号 G11C7/12 主分类号 G11C7/12
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