发明名称 Phase locked loop for generating an output signal
摘要 A phase locked loop (PLL) for generating an output signal according to an input signal is disclosed. The PLL of the present invention includes a detector for generating a detection signal according to the logical difference between the input signal and a feedback signal, a signal mixer electrically connected to the detector for generating a control signal according to the detection signal and a mixing reference signal, a filtering device electrically connected to the signal mixer for generating an adjust signal according to the control signal, a controllable oscillator electrically connected to the filtering device for generating the output signal according to the adjust signal, and a frequency divider electrically connected to the controllable oscillator for generating the feedback signal and the mixing reference signal according to the output signal. The frequency of the output signal is at least twice the frequency of the input signal.
申请公布号 US7274636(B2) 申请公布日期 2007.09.25
申请号 US20040905132 申请日期 2004.12.17
申请人 MEDIATEK INCORPORATION 发明人 CHEN HONG-CHING;WU WEN-YI
分类号 G11B7/00;G11B5/09;G11B20/14;G11B27/19;G11B27/24;H03L7/085;H03L7/089;H03L7/191 主分类号 G11B7/00
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